1. Technical Field
The present invention relates to ferroelectric memory devices.
2. Related Art
Japanese laid-open patent application JP-A-2002-157876 (patent document 1) describes a typical ferroelectric memory. In the ferroelectric memory described in the above document, bit lines connected to a 2T2C cell for one bit for generating reference voltages are connected to a sense amplifier through a level shift circuit having P-channel source followers composed of PMOS transistors, and the sense amplifier takes voltages that have passed through the level shift circuit as reference voltages (see the third embodiment described in the patent document 1).
However, the ferroelectric memory described above uses the voltages that have passed through the level shift circuits as reference voltages, and thus has a problem in which its read-out margin is relatively small. Also, in the ferroelectric memory described above, the level shift circuit needs to be connected not only to a bit line to which the cell for generating reference voltages is connected, but to another bit line that does not essentially require the level shift circuit. This causes a problem of an increased layout area.